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Verilog User Testbench Procedures
F
Following is a list of the supported tasks in the Verilog user testbench. Actel recommends that you examine the
testbench.v file to understand how to use these tasks.
// PCI configuration cycles
config_write (SLOT,CADDRESS,COUNT);
config_read (SLOT,CADDRESS,COUNT);
// PCI memory cycles
memory_write (ADDRESS,COUNT,PCI64);
memory_read (ADDRESS,COUNT,PCI64);
compare_data (ERRCOUNT,COUNT);
// Writes and reads to and from the core backend interface
be_write (BADDRESS,WDATA, BYTEEN);
be_read (BADDRESS,RDATA);
The parameters to the above tasks are described in Table F-1 and Table F-2 on page 145 . Data for the PCI
configuration and PCI memory read and write cycles is passed in the pciwdata and pcirdata global arrays rather than
through the task parameters.
Table F-1 · Global Descriptions
Globals
pciwdata
pcirdata
Type
reg [31:0] [0:31]
reg [31:0] [0:31]
Description
This is an array in which the user sets up the data that will be written before calling the memory_write or
config_write tasks. For 64-bit operations, the lower DWORD is specified in the odd addresses and the
upper DWORD in the even addresses.
This is an array by which the memory_read and config_read functions return data. For 64-bit operations,
the lower DWORD is specified in the odd addresses and the upper DWORD in the even addresses.
Table F-2 · Parameter Descriptions
Parameters
SLOT
CADDRESS
COUNT
ADDRESS
PCI64
ERRCOUNT
Type
reg [2:0]
reg [7:0]
reg [7:0]
reg [31:0]
reg
inout reg [31:0]
Description
PCI slot number to use for configuration cycles. When 0, will set the eight upper address bits to
01h. When 1, will set the eight upper address bits to 02h, etc. The testbench connects address bit 25
to the core IDSEL input; therefore, the slot number should be set to 1.
Configuration space address
Number of DWORDs to be written, read, or compared. If 64-bit operation is enabled, this must be
an even number. The maximum count is thirty-two 32-bit transfers or sixteen 64-bit transfers.
Memory space address
When 1, the testbench will request a 64-bit transfer.
The compare routine will increment this value if it detects any errors. At the end of a test sequence,
it can indicate the total number of errors.
v4.0
145
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